In a conventional compiler, as a technology for reducing the number of times of instruction executions, a technology of removing partial redundancy is used (refer to nonpatent literature 1). According to this technology, for example, when an instruction executed at a merger destination of control flows and an instruction executed at one of merger origins of the control flows are redundant, the instruction at the merger destination is moved to the other of the merger origins and thus the number of the instruction executions can be reduced.
[Nonpatent Literature 1]
J. Knoop, O. Ruthing and B. Steffen, Lazy code motion, In PLDI '92, p. 224-234, 1992. Japanese title “Lazy code movement”
However, according to the foregoing technology, while the number of times of executing respective instructions can be reduced, the instructions cannot be moved to other basic blocks in order to generate a synthesis instruction for efficiently executing processings from a plurality of instructions by synthesis. For example, in a computer of a 64-bit architecture, when two load instructions for reading 32-bit data from addresses adjacent to each other are executed in two basic blocks, respectively, it was impossible to perform optimization in which one 32-bit load instruction is moved to another basic block in order to synthesize the two 32-bit load instructions to obtain a 64-bit load instruction.